Comparative Study and Implementation of Vedic Multiplier for Reversible Logic Based ALU

Authors:

Shaveta Thakral (Manav Rachna International University, Faridabad)

Dipali Bansal (Manav Rachna International University, Faridabad)

Keywords: Vedic multiplier, Reversible logic, ALU, Verilog HDL, Quantum cost

Abstract:

ALU is fundamental building block of modern computing environment supported by embedded processors. The demand for low power consumption & high processing speed has been increasing in modern scientific computers and signal processing applications. Speed of ALU depends mainly on multipliers and multipliers are generally slowest in speed. Therefore reversible logic based Vedic Multiplier need to be designed for the implementation of ALU to add on high speed and low power requirements. The main aim of this paper is to present critical review of existing Vedic multipliers The existing Vedic multipliers are coded in Verilog HDL, synthesized and simulated using EDA (Electronic Design Automation) tool-Xilinx ISE design suit 14.2. Finally the results are compared for all existing multipliers in terms of ancillary inputs, garbage outputs, number of reversible logic gates and quantum cost.

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