Comparative Analysis of D Flip Flop using various Submicron Technologies

Issue: Vol.9 No.1

Authors:

Ila Chaudhary (Manav Rachna International University, Faridabad)

Amana Yadav (Manav Rachna International University, Faridabad)

Dipali Bansal (Manav Rachna International University, Faridabad)

Keywords: D Flip flop, Complementary Metal Oxide Semiconductor (CMOS), Low power, Transmission Gate (TG) and Tanner Tool

Abstract:

As technology is getting scale down so delay, power and areaperform a critical role in the designing and calculation of numerous digitalcircuit applications. Portable devices are in demand now a day’s hence designingof low power devices is very necessary. So, detail analysis of digital circuits interms of power, delay, performance, and area is essential. D Flip Flop is one ofthe important digital circuits which have enormous applications in variousdigital designs. Hence, this paper presents performance analysis of D Flip flopcircuit using various technologies and their comparative analysis in terms ofpower dissipation and delay. This circuit has been designed using Tanner EDAtool with different technologies (i.e. 45nm, 90nm and 180nm). The powerdissipation and delay of 45nm technology is less than the other twotechnologies.

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References:

[1] Saradindu Panda, A.banerjee, B.maji, “Power and Delay comparison in between different types of full adder circuits”, International journal of advanced research in Electrical, Electronics and instrumentation engineering, Vol. 1, No. 3, Sept. 2012.

[2] M. Sharma, K.G. Sharma , T. Sharma, B.P Singh, N. Arora, SET D Flip Flop design for Portable Application, Indian International conference on Power electronics, IEEE, pp. 1-5, 2011.

[3] M. Sharma, K.G. Sharma , T. Sharma, B.P Singh, N. Arora, Modified SETD-Flip Flop Design for Low-Power VLSI Applications, Indian International conference on Devices and Communication ,IEEE, pp. 1-5, 2011

[4] M. Sharma , A. Noor , S.C. Tiwari , K. Singh, An Area and Power Efficient Design of Single Edge Triggered D-Flip Flop, International conference on Advances in Recent Technologies in Communication and Computing, pp 478-481, 2009.

[5] M. Alitio, M. Palumbo , Modelling and Optimized Design of Current Mode MUX/XOR and D Flip , IEEE
Transactions on Circuits and Systems II: Analog and Digital Signal Processing ( Volume: 47, Issue: 5, May 2000 )

[6] Flop, IEEE Transaction on Circuits and Systems—II, Vol. 47, No. 5, pp. 452-462, May, 2000.

[7] B. Chinnarai. , B Fransis , Y. Apparao , Design of A Low Power Flip-Flop Using CMOS Deep Submicron
Technology International Journal of Electronics Signals and Systems (IJESS) ISSN: 2231-5969, Vol-2 Iss-1, pp. 95-99, 2012.

[8] Sung-Mo Kang , Yusuf Leblebici, CMOS Digital Integrated Circuits , Tata McGraw-Hill publication New Delhi, pp. 343-347, 2010.

[9] Yu Chien-Cheng Design of Low-Power Double EdgeTriggered Flip-Flop Circuit 2007, Second IEEE  Conference on Industrial Electronics and Applications ,23-25 May 2007 pp 2054-2057.

[10] Niel H. E. Weste, David Harris, Ayan Benerjee, CMOS VLSI Design , Pearson Education, New Delhi, pp. 16, 2009.