Stress Generation Techniques in Advanced CMOS

Authors:

Meenakshi Gupta (Manav Rachna College of Engineering, Faridabad)

Abstract:

Process-induced strained silicon device technology is being adopted by the semiconductor industry to enhance the performance of the devices in the nanometer realm. The prime area of research is to explore different ways to maximize the desirable strain in the device channel. Difficulties also exist with scaling strain to future technology generations. The stress is a function of different parameters like geometry of the structure, boundary conditions, material parameters, process flow, etc. In this paper, the understanding and issues of MOSFET performance enhancement using strained silicon devices will be discussed. Various processes of strain induction will be reviewed with uniaxial and biaxial stress induction techniques. A range of issues such as stress dependence on critical dimension scaling, effect of buffer layer and silicides etc. are required to be given consideration. At last, the advanced strained silicon on insulator (SSOI) device will be considered as a case of technological importance.

References:

1. H. Randell, “Applications Of Stress From Boron Doping And Other Challenges In Silicon Technology,” Master’s Thesis. University of Florida, 2005.

2. M. Bohr, Intel’s 90 nm Logic Technology Using Strained Silicon Transistors, Presentation, Dec. 2003.

3. S.E. Thompson, M. Armstrong, et al, “A Logic Nanotechnology Featuring Strained-Silicon,” IEEE Electron Device Letters, Vol. 25, No. 4, pp. 191-193, April 4, 2004.

4. S. I to, H. Namba, T. Hirata, K. Ando, S. Koyama, N. Ikezawa, T. Suzuki, T. Saitoh, T. Horiuchi , “Effect of Mechanical Stress Induced by Etch-stop Nitride: Impact on Deep-submicron Transistor Performance,” Microelectronics Reliability, Vol. 42, pp. 201-209, February 2002.

5. A. Al-Bayati, L. Washington, L. Xia, M. Balseanu, Z. Yuan, M. Kawaguchi, F. Nouri, R. Arghavani, “Production Processes for Inducing Strain in CMOS Channels,” Semiconductor Fabtech, 26th Edition, 2005.

6. N. Mohta and S.E. Thompson, “Strained Si-The Next Vector to Extend Moore’s Law,” To be published in IEEE Circuits and Devices Magazine, 2005.

7. S. M. Cea, M. Armstrong, et al, “Front End Stress Modeling for Advanced Logic Technologies,” IEDM, San Francisco, CA, 2004.

8. K. P. Liew, R.A. Bernstein, C. V. Thompson, “Stress Development and Relaxation during Reactive Film Formation of Ni2Si,” J. Mater. Res., Vol. 19, No. 2, February 2004.

9. S. L. Hsia, T. Y. Tan, P. Smith, G. E. McGuire, “Resistance and Structural Stabilities of Epitaxial CoSi2 Films on (001) Si Substrates,” J. Appl. Phys., Vol. 72, No. 5, September 1992.

10. Nirav Shah, “Stress Modeling of Nanoscale MOSFETs”, University of Florida , 2005

11. C. Zhi-Yuan, M. T. Currie, C. W. Leitz, G. Taraschi, E. A. Fitzgerald, J. L. Hoyt, D. A. Antoniadas, “Electron Mobility Enhancement in Strained-Si n-MOSFETs Fabricated on SiGe-On-Insulator (SGOI) Substrates,” IEEE Electron Device Letters, Vol. 22, No. 7, 2001.

12. J. L. Hoyt, H. M. Nayfeh, et al, “Strained Silicon MOSFET Technology,” IEDM Technical Digest, Dec. 2002.

13. K. Rim, K. Chan, et al, “Fabrication and Mobility Characteristics of Ultra-thin Strained Si Directly on Insulator (SSDOI) MOSFETs,” IEDM Technical Digest, Dec. 2003.

14. S.H. Christiansena, et al, “Strained Silicon on Insulator (SSOI) by Waferbonding,” Materials Science in Semiconductor Processing, Vol. 8, 2005. Soitec Inc., last accessed July 2005, http://www.soitec.com/