Booth Modified RNS Multiplier in RNS to Binary Code Converator Using {2P+1 2P, 2p-1}

Issue: Vol.6 No.2

Authors:

P. Charantej (VIT University, Vellore)

R. Dhanabal (VIT University, Vellore)

SS Kerur

Harish Kittu

Keywords: Code converters, field-programmable gate arrays (FPGAs), residue arithmetic,Soc encounter, cadence.

Abstract: 

A RNS reverse convertor moduli set {2p+1,2p,2p-1} is proposed in this paper. Chinese Remainder Theorem is simplified to get a reverse converter that uses mod-{2p-1} operations. The proposed architecture reduces the burden of explicit use of moduli operation in conversion process and we prove that theoretically speaking it outperforms state of the art equivalent converters. In order to restrict the range we makes use of radix-8 booth modified rns multiplier in the proposed converter on cyclone2 FPGA. When compare to other convertors, this architecture saves power, area, delay and cost.

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